1. Field of the Invention
The present invention relates to integrated semiconductor device fabrication and apparatus therefore. More specifically, the invention relates to improved annealing and reflow methods and apparatus for annealing and reflowing.
2. Description of the Invention
Semiconductor devices are normally encapsulated in a glass or similar passivation layer in order to chemically, mechanically and electrically insulate the enclosed array from the environments that the device will be subjected to before, during and after the time the array or device is tested and/or used for its chosen task. Glasses such as Borophosphosilicate glass (BPSG) are frequently used as a passivation layer or interlayer dielectric film because (1) the BPSG layer has a substantially lower reflow temperature than most other passivation materials, and (2) the presence of boron and phosphorus atoms in approximately equal concentrations in the layer insures that such material will not produce a net N type or P type average carrier density of substantial magnitude so as to cause inversion or other problems. However, BPSG has problems. BPSG is normally deposited, annealed and reflowed in a tube furnace made of quartz. The furnace consists of an elongated tube that is open at one end for introducing semiconductor wafers, and has a single gas inlet on the opposite end. The wafers are positioned vertically, in spaced relation, on a suitable support and placed in the furnace tube. A loose fitting enclosure is placed over the open end and a heated gas introduced into the heated furnace through the gas inlet. The gas flows longitudinally down the length of the tube furnace past the wafers which are positioned with their major or flat surfaces perpendicular to the flow. With this apparatus, it has been observed that during reflow and annealing operations, BPO.sub.4 crystals have a tendency to form by the re-crystallization of BPSG layer, particularly near the center of the wafers. This leads to problems, more particularly as the dimensions of the circuitry on the wafer are reduced in order to obtain greater miniaturization. The BPO.sub.4 crystals 16 may form about contact openings 10, as illustrated in the cross sectional view of a device in FIG. 1. Since BPO.sub.4 crystals can not be removed by either wet or dry etch, they will cause the poor contact opening and/or metal bridging. Bridging is illustrated in FIGS. 1 and 2 when BPO.sub.4 crystals 16 form an electrically conductive path between adjacent conductive stripes 12 and 14.